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| TN2524 N-Channel Enhancement-Mode Vertical DMOS FET Features Low threshold -- 2.0V max High input impedance Low input capacitance -- 125pF max Fast switching speeds Low ON-resistance Free from secondary breakdown Low input and output leakage Complementary N and P-channel devices General Description This low threshold, enhancement-mode (normally-off) transistor utilizes a vertical DMOS structure and Supertex's well-proven, silicon-gate manufacturing process. This combination produces a device with the power handling capabilities of bipolar transistors and the high input impedance and positive temperature coefficient inherent in MOS devices. Characteristic of all MOS structures, this device is free from thermal runaway and thermally-induced secondary breakdown. Supertex's vertical DMOS FETs are ideally suited to a wide range of switching and amplifying applications where very low threshold voltage, high breakdown voltage, high input impedance, low input capacitance, and fast switching speeds are desired. Applications Logic level interfaces -- ideal for TTL and CMOS Solid state relays Battery operated systems Photo voltaic devices Analog switches General purpose line drivers Telecom switches Ordering Information BVDSS/BVDGS (V) RDS(ON) max () VGS(th) max (V) ID(ON) min (A) Package Options TO-243AA (SOT-89) TN2524N8-G Die* TN2524ND 240 6.0 2.0 1.0 -G indicates package is RoHS compliant (`Green') * MIL visual screening available. Pin Configuration DRAIN Absolute Maximum Ratings Parameter Drain-to-source voltage Drain-to-gate voltage Gate-to-source voltage Operating and storage temperature Soldering temperature* O SOURCE Value BVDSS BVDGS 20V -55 C to +150OC 300 C O DRAIN GATE TO-243AA (SOT-89) (N8) Product Marking TN5CW Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied. Continuous operation of the device at the absolute rating level may affect device reliability. All voltages are referenced to device ground. * Distance of 1.6mm from case for 10 seconds. W = Code for week sealed TO-243AA (SOT-89) (N8) TN2524 Thermal Characteristics Package TO-243AA (SOT-89) (continuous)* (A) ID (pulsed) (A) ID Power Dissipation @TA = 25OC (W) jc ( C/W) O ja ( C/W) O IDR* (A) IDRM (A) 0.36 2.0 1.6() 15 78() 0.36 2.0 Notes: * ID (continuous) is limited by max rated Tj . Mounted on FR5 board, 25mm x 25mm x 1.57mm. Electrical Characteristics (T Sym BVDSS VGS(th) VGS(th) IGSS IDSS Parameter A = 25OC unless otherwise specified) Min 240 0.6 - Typ 1.9 2.8 4.0 4.0 600 65 35 10 300 Max 2.0 -5.0 100 10 1.0 6.0 6.0 1.4 125 70 25 10 10 20 20 1.8 - Units V V O Conditions VGS = 0V, ID = 2.0mA VGS = VDS, ID= 1.0mA VGS = 20V, VDS = 0V VGS = 0V, VDS = Max Rating VGS = 0V, VDS = 0.8 Max Rating, TA = 125C VGS = 4.5V, VDS = 25V VGS = 10V, VDS = 25V VGS = 4.5V, ID = 250mA VGS = 10, ID = 0.5A VGS = 10V, ID = 0.5A VGS = 0V, VDS = 25V, f = 1.0MHz VDD = 25V, ID = 1.0A, RGEN = 25 Drain-to-source breakdown voltage Gate threshold voltage Change in VGS(th) with temperature Gate body leakage Zero gate voltage drain current mV/ C VGS = VDS, ID= 1.0mA nA A mA A %/ C O 0.5 1.0 300 - ID(ON) RDS(ON) RDS(ON) GFS CISS COSS CRSS td(ON) tr td(OFF) tf VSD trr ON-state drain current Static drain-to-source ON-state resistance Change in RDS(ON) with temperature Forward transductance Input capacitance Common source output capacitance Reverse transfer capacitance Turn-ON delay time Rise time Turn-OFF delay time Fall time Diode forward voltage drop Reverse recovery time mmho VDS = 25V, ID = 0.5A pF ns V ns VGS = 0V, ISD = 1.0A VGS = 0V, ISD = 1.0A Notes: (1) All D.C. parameters 100% tested at 25OC unless otherwise stated. (Pulse test: 300s pulse, 2% duty cycle.) (2) All A.C. parameters sample tested. Switching Waveforms and Test Circuit VDD 10V 90% INPUT 0V 10% t(ON) PULSE GENERATOR t(OFF) tr td(OFF) tF RL OUTPUT RGEN td(ON) VDD 10% 10% INPUT D.U.T. OUTPUT 0V 90% 90% 2 TN2524 Typical Performance Curves 3 TN2524 Typical Performance Curves (cont.) BVDSS Variation with Temperature 10 1.1 8 On-Resistance vs. Drain Current V GS = 4.5V VGS = 10V BVDSS (normalized) RDS(ON) (ohms) -50 0 50 100 150 6 1.0 4 2 0.9 0 0 1 2 3 4 5 Tj ( C) Transfer Characteristics 3.0 ID (amperes) V(th) and RDS Variation with Temperature 2.4 1.4 VDS = 25V 2.5 25C 1.2 ID (amperes) 2.0 V(th) @ 1mA 1.0 1.6 1.5 1.2 0.8 0.8 1.0 0.5 0.6 0 0 2 4 6 8 10 -50 0 50 100 150 0.4 VGS (volts) Capacitance vs. Drain-to-Source Voltage 200 10 Tj ( C) Gate Drive Dynamic Characteristics f = 1MHz 8 150 VDS = 10V C (picofarads) VGS (volts) 6 100 VDS = 40V 4 150 pF CISS 50 COSS CRSS 0 0 10 20 30 40 2 0 0 0.4 63pF 0.8 1.2 1.6 2.0 VDS (volts) QG (nanocoulombs) 4 RDS(ON) (normalized) VGS(th) (normalized) TA = -55C 150C RDS(ON) @ 10V, 0.5A 2.0 TN2524 3-Lead TO-243AA (SOT-89) Package Outline (N8) D D1 4 C EH E1 1 L b e 2 3 b1 e1 A Top View Side View Symbol MIN Dimensions (mm) NOM MAX A 1.40 1.60 b 0.44 0.56 b1 0.36 0.48 C 0.35 0.44 D 4.40 4.60 D1 1.62 1.83 E 2.29 2.60 E1 2.13 2.29 e 1.50 BSC e1 3.00 BSC H 3.94 4.25 L 0.89 1.20 JEDEC Registration TO-243, Variation AA, Issue C, July 1986. Drawings not to scale. (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to http://www.supertex.com/packaging.html.) Doc.# DSFP-TN2524 A101207 5 |
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